1. Technical Field
This disclosure generally relates to digital memory devices or circuits, and more specifically relates to efficient data eye calibration of memory devices such as double data rate (DDR) memory.
2. Background Art
High speed data links are often used to interface between a memory controller and a double data rate (DDR) synchronous dynamic random access memory (SDRAM) device. A DDR SDRAM interface may receive aligned data (DQ) and read data strobe (DQS) signals from a DDR SDRAM device for transfer to a memory controller. The DDR SDRAM interface or memory controller is responsible for providing the appropriate DQ-DQS timing relationship to provide, for example, an adequate setup and hold time margin within a data valid window. Various methods have been developed for calibrating a data valid window to maintain the read data strobe (DQS) substantially in the center of a defined data valid window for DDR memory applications. Data calibration was first done in the time domain. Subsequently, data calibration has been done in two dimensions that include the time domain and reference voltage (Vref) training. Calibrating the data valid window is sometimes called data “eye” training.
DDR memory calibration or data eye training may be performed at system boot by a basic input/output system (BIOS), a unified extensible firmware interface (UEFI), or a memory controller. Data eye training may be used to place a memory data strobe within the data eye for a given memory cycle. By performing a two-dimensional analysis, it is possible to adjust and/or select the operating Vref(s) for a DDR memory by making tradeoffs between optimized timing and Vref voltage margins. Data eye training may occur on a DRAM by DRAM basis, on a rank by rank basis, on a channel by channel basis, or across all byte lanes.